Logic / ESL Synthesis Design Services offered by Coral9 Consulting
Logic synthesis is a process by which an abstract form of desired circuit behavior, typically at register transfer level (RTL), is turned into a design implementation in terms of logic gates, typically by a computer programme called a synthesis tool. Common examples of this process include synthesis of HDLs, including VHDL and Verilog.
High-level synthesis or Behavioral synthesis
Today, high-level synthesis, also known as ESL synthesis and behavioral synthesis, essentially refers to circuit synthesis from high level Languages like ANSI C/C++ or SystemC etc. to RTL Level, whereas Logic Synthesis refers to synthesis from structural or functional description to RTL.
Multi-Level logic minimization
Typical practical implementations of a logic function utilize a multi-level network of logic elements. Starting from an RTL description of a design, the synthesis tool constructs a corresponding multilevel Boolean network.
Next, this network is optimized using several technology-independent techniques before technology-dependent optimizations are performed. Finally, technology-dependent optimization transforms the technology-independent circuit into a network of gates in a given technology. The simple cost estimates are replaced by more concrete, implementation-driven estimates during and after technology mapping. Mapping is constrained by factors such as the available gates (logic functions) in the technology library, the drive sizes for each gate, and the delay, power, and area characteristics of each gate.